In digital communication networks, clock signals--referred to below as network clock signals--are communicated to the individual network components such as, for example, switching equipment either separately or within the information flow. In switching equipment such as, for example, private branch exchange systems, the received network clock signals are usually not directly utilized for clock control of the individual components of the switching equipment since, given outage of the network clock signals, the switching equipment would no longer be controllable, or would assume an undefined operating condition. For this reason, the received network clock signals are conducted to a phase-locked loop in which internal clock signals are formed and are communicated to the individual components of a subscriber station.
The following functions must be realized in such a phaselocked loop:
internal clock pulses are generated in an internal voltage-controlled oscillator - referred to below as a VCO oscillator; PA1 the frequency of the network clock signals is matched to the frequency of the internal clock signals; and PA1 the internal VCO oscillator is controlled such that the phases of the network clock signals and of the internal clock signals coincide in order to
1. be able to directly process information communicated from the communications network in the switching equipment, and PA0 2. avoid a phase skip in one of the internal clock signals given outage of the network clock signals.
In addition to integrated circuits, microprocessors of suitable scope are being utilized to an increasing degree in phase-locked loops. The publication "Proceedings of 1979 ISCAS", pages 804 through 805 incorporated herein discloses a phase-locked loop that first, exhibits the function features set forth above and, second, is equipped with a microprocessor system. This phase-locked loop is composed of a digital phase comparator, of a digitally controlled oscillator, of a control means, and of two divider means. The frequency of the supplied network clock signals is reduced in the first divider means. These network clock signals having a modified frequency are subsequently forwarded to a digital phase comparison means. The phase comparison means is provided with a phase comparator and with a counter. The internal clock pulses generated in a digitally controlled oscillator are additionally supplied to the phase comparison means via the second divider means. The divider means are dimensioned such that the frequency of the network clock signals present at the phase comparator approximately coincides with that of the internal clock signals. The two clock signals are compared in the phase comparator in terms of their phase relation; and the result of the comparison is supplied to the counter. The internal clock signals are also communicated to the counting input of the counter. When the phases of the two clock signals deviate from one another, then internal clock signals are read into the counter and are counted. The result of the count is forwarded to a control means realized by a microprocessor system. The counter readings representing the phase deviations are identified in this control means, are filtered with a low-pass filter, and are conducted to an externally arranged D/A converter as digital voltage values. The analog output voltages output by the D/A converter control a VCO oscillator such that the internal clock signals generated by the VCO oscillator coincide with the network clock signals in terms of their phase relation. Together, the VCO oscillator and the D/A converter form the digitally controlled oscillator.
It proceeds from the above noted publication that the individual system components of the control circuit such as the phase comparator, counter, oscillator and D/A converter are not integrated into the control means. Also, the publication contains no references as to how the individual hardware components, and particularly the phase comparator, can be realized. Furthermore, the phase-locked loop can only be adapted to different network clock and VCO clock signal frequencies by modifying or replacing hardware components.